ADSP-2191MKSTZ-160

PERFORMANCE FEATURES 6.25 ns Instruction Cycle Time, for to 160 MIPS
Sustained Performance ADSP-218x Family Code Compatible with the Same

Easy to Use Algebraic Syntax Single-Cycle Instruction Execution Single-Cycle Context Switch between Two Sets of Com-

putation and Memory Instructions Instruction Cache Allows Dual Operand Fetches in Every
Multifunction Instructions Pipelined Architecture Supports Efficient Code
Code Efficiency Architectural Enhancements beyond ADSP-218x Family

are Supported with Instruction Set Extensions for Added Registers, and Peripherals Flexible Power Management with User-Selectable Power-Down and Idle Modes

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INTEGRATION FEATURES 160K Bytes On-Chip RAM Configured as 32K Words 24-Bit
Memory RAM and 32K Words 16-Bit Memory RAM Dual-Purpose 24-Bit Memory for Both Instruction and
Data Storage Independent ALU, Multiplier/Accumulator, and Barrel

Shifter Computational Units with Dual 40-Bit Accumulators Unified Memory Space Allows Flexible Address Generation, Using Two Independent DAG Units Powerful Program Sequencer Provides Zero-Overhead Looping and Conditional Instruction Execution Enhanced Interrupt Controller Enables Programming of Interrupt Priorities and Nesting Modes

SYSTEM INTERFACE FEATURES Host Port with DMA Capability for Glueless or 16-Bit
Host Interface 16-Bit External Memory Interface for to 16M Words of
Addressable Memory Space Three Full-Duplex Multichannel Serial Ports, with

Support for H.100 and to 128 TDM Channels with A-Law and -Law Companding Optimized for Telecommunications Systems Two SPI-Compatible Ports with DMA Support UART Port with DMA Support 16 General-Purpose I/O Pins with Integrated Interrupt Support Three Programmable Interval Timers with PWM Generation, PWM Capture/Pulsewidth Measurement, and External Event Counter Capabilities to 11 DMA Channels Can Be Active at Any Given Time for High I/O Throughput On-Chip Boot ROM for Automatic Booting from External or 16-Bit Host Device, SPI ROM, or UART with Autobaud Detection Programmable PLL Supports to 32 Input Frequency Multiplication and Can Be Altered during Runtime IEEE JTAG Standard 1149.1 Test Access Port Supports On-Chip Emulation and System Debugging 2.5 V Internal Operation and 3.3 V I/O 144-Lead LQFP and 144-Ball Mini-BGA Packages

DSP Core Architecture.3 DSP Peripherals Architecture.4 Memory Architecture.5 Interrupts.6 DMA Controller.7 Host Port.7 DSP Serial Ports (SPORTs).8 Serial Peripheral Interface (SPI) Ports.9 UART Port.9 Programmable Flag (PFx) Pins.9 Low Power Operation.10 Clock Signals.11 Reset.11 Power Supplies.11 Booting Modes.11 Bus Request and Bus Grant.12 Instruction Set Description.13 Development Tools.13 Additional Information.15 PIN FUNCTION DESCRIPTIONS.15 SPECIFICATIONS.18 ABSOLUTE MAXIMUM RATINGS.19 ESD SENSITIVITY.19 Power Dissipation.19 TIMING SPECIFICATIONS.20 Output Drive Currents.40 Power Dissipation.40 Test Conditions.40 Environmental Conditions.41 144-Lead LQFP Pinout.43 144-Lead Mini-BGA Pinout.45 OUTLINE DIMENSIONS.47 ORDERING GUIDE.48 Revision History.48

GENERAL DESCRIPTION The ADSP-2191M DSP is a single-chip microcomputer optimized for digital signal processing (DSP) and other high speed numeric processing applications.

The ADSP-2191M combines the ADSP-219x family base architecture (three computational units, two data address generators, and a program sequencer) with three serial ports, two SPI-compatible ports, one UART port, a DMA controller, three programmable timers, general-purpose Programmable Flag pins, extensive interrupt capabilities, and on-chip program and data memory spaces.

The ADSP-2191M architecture is code-compatible with DSPs of the ADSP-218x family. Although the architectures are compatible, the ADSP-2191M architecture has a number of enhancements over the ADSP-218x architecture. The enhancements to computational units, data address generators, and program sequencer make the ADSP-2191M more flexible and even easier to program.

Indirect addressing options provide addressing flexibility-- premodify with no update, pre- and post-modify by an immediate 8-bit, two's-complement value and base address registers for easier implementation of circular buffering.

The ADSP-2191M integrates 64K words of on-chip memory configured as 32K words (24-bit) of program RAM, and 32K words (16-bit) of data RAM. Power-down circuitry is also provided to reduce power consumption. The ADSP-2191M is available in 144-lead LQFP and 144-ball mini-BGA packages.

Fabricated in a high speed, low power, CMOS process, the ADSP-2191M operates with 6.25 ns instruction cycle time (160 MIPS). All instructions, except single-word instructions, execute in one processor.

The ADSP-2191M's flexible architecture and comprehensive instruction set support multiple operations in parallel. For example, in one processor cycle, the ADSP-2191M can:

Generate an address for the next instruction fetch Fetch the next instruction Perform one or two data moves Update one or two data address pointers Perform a computational operation

These operations take place while the processor continues to:

Receive and transmit data through two serial ports Receive and/or transmit data from a Host Receive or transmit data through the UART Receive or transmit data over two SPI ports Access external memory through the external memory

DSP Core Architecture The ADSP-2191M instruction set provides flexible data moves and multifunction (one or two data moves with a computation) instructions. Every single-word instruction can be executed in a single processor cycle. The ADSP-2191M assembly language

uses an algebraic syntax for ease of coding and readability. A comprehensive set of development tools supports program development.

The functional block diagram on Page 1 shows the architecture of the ADSP-219x core. It contains three independent computational units: the ALU, the multiplier/accumulator (MAC), and the shifter. The computational units process 16-bit data from the register file and have provisions to support multiprecision computations. The ALU performs a standard set of arithmetic and logic operations; division primitives are also supported. The MAC performs single-cycle multiply, multiply/add, and multiply/subtract operations. The MAC has two 40-bit accumulators, which help with overflow. The shifter performs logical and arithmetic shifts, normalization, denormalization, and derive exponent operations. The shifter can be used to efficiently implement numeric format control, including multiword and block floating-point representations.

Register-usage rules influence placement of input and results within the computational units. For most operations, the computational units' data registers act as a data register file, permitting any input or result register to provide input to any unit for a computation. For feedback operations, the computational units let the output (result) of any unit be input to any unit on the next cycle. For conditional or multifunction instructions, there are restrictions on which data registers may provide inputs or receive results from each computational unit. For more information, see the ADSP-219x DSP Instruction Set Reference.

A powerful program sequencer controls the flow of instruction execution. The sequencer supports conditional jumps, subroutine calls, and low interrupt overhead. With internal loop counters and loop stacks, the ADSP-2191M executes looped code with zero overhead; no explicit jump instructions are required to maintain loops.

Two data address generators (DAGs) provide addresses for simultaneous dual operand fetches (from data memory and program memory). Each DAG maintains and updates four 16-bit address pointers. Whenever the pointer is used to access data (indirect addressing), it is pre- or post-modified by the value of one of four possible modify registers. A length value and base address may be associated with each pointer to implement automatic modulo addressing for circular buffers. Page registers in the DAGs allow circular addressing within 64K-word boundaries of each of the 256 memory pages, but these buffers may not cross page boundaries. Secondary registers duplicate all the primary registers in the DAGs; switching between primary and secondary registers provides a fast context switch.

Efficient data transfer in the core is achieved with the use of internal buses: