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DIP-20
FSC
0630AB
Octal D Flip-Flop with 3-STATE Outputs; Package: DIP; No of Pins: 20; Container: Rail
Stock:10000
Minimum:3
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SOP14
FSC
The VHC74 is an advanced high speed CMOS Dual D-Type Flip-Flop fabricated with silicon gate CMOS technology. It achieves the high speed operation similar to equivalent Bipolar Schottky TTL while maintaining the CMOS low power dissipation. The signal level applied to the D input is transferred to the Q output during the positive going transition of the CK pulse. CLR# and PR# are independent of the CK and are accomplished by setting the appropriate input LOW. An input protection circuit ensures that 0V to 7V can be applied to the input pins without regard to the supply voltage. This device can be used to interface 5V to 3V systems and two supply systems such as battery backup. This circuit prevents device destruction due to mismatched supply and input voltages.
Description: The 74VHC74M is a high-speed CMOS dual D-type flip-flop with reset and complementary outputs. Features: High Speed Operation Low Power Consumption High Noise Immunity Low Input Curr
Stock:10000
Minimum:3
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Description: 74F377SJ is a 20-pin SOP (Small Outline Package) logic device manufactured by Fairchild Semiconductor. It is a 4-bit register with 3-state outputs. Features: 4-bit register with 3-state
Stock:10000
Minimum:2
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TSSOP-14
Texas Instruments
Dual D-type flip-flop with set and reset; positive-edge trigger - Description: Dual D-Type Flip-Flop with Set and Reset; Positive-Edge Trigger ; Fmax: 170 @ 5 V MHz; Logic switching levels: CMOS ; Output drive capability: +/- 8 mA ; Power dissipation considerations: Low Power or Battery Applications ; Propagation delay: 3.7@5 V ns; Voltage: 2.0-5.5 V; Package: SOT402-1 TSSOP14; Container: Reel Pack, SMD, 13"
Stock:10000
Minimum:2
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DIP-14
National Semiconductor
Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flops with Clear and Complementary Outputs
Stock:10000
Minimum:2
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Stock:10000
Minimum:3
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Description: The DM7474N is a dual negative-edge triggered D-type flip-flop with independent data, set, and reset inputs. Features: High-Speed Performance: tPD = 10 ns (typical) Low Power Cons
Stock:10000
Minimum:2
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DIP14
National Semiconductor
Dual Master-Slave J-K Flip-Flops with Clear and Complementary Outputs
Description: The DM7473N is a dual 4-bit static flip-flop with common Clock and Master Reset. Features: - Inputs include Clock, Master Reset, Set and Reset for each flip-flop - Outputs from each flip
Stock:10000
Minimum:3
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Description: The CD4027BPWR is a dual J-K flip-flop with individual J, K, clock, preset, clear, and complementary outputs. Features: Low power consumption High noise immunity High speed operation
Stock:10000
Minimum:2
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SOP-20
Texas Instruments
0423
OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS WITH 3-STATE OUTPUTS
SN74ACT374NSR is a octal transparent D-type latch manufactured by Texas Instruments. It is a 20-pin small outline package (SOP). Description: The SN74ACT374NSR is an octal transparent D-type latch th
Stock:10000
Minimum:2
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DIP-20
National Semiconductor
88+
Octal D-Type Flip-Flop with Clock Enable; Package: DIP; No of Pins: 20; Container: Rail
Stock:10000
Minimum:2
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Stock:10000
Minimum:2
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SOP14
Ns/fsc
00+
Octal D Flip-Flop with 3-STATE Outputs; Package: DIP; No of Pins: 20; Container: Rail
Stock:10000
Minimum:13
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DIP-14
Ti/mot
500mA, 5V,±4% Tolerance, Negative Voltage Regulator, Ta = 0°C to +125°C; Package: TO-220, SINGLE GAUGE; No of Pins: 3; Container: Rail; Qty per Container: 50
Description: The SN74LS73AN is a dual positive edge-triggered J-K flip-flop with individual J, K, clock, set and reset inputs, and complementary Q and Q outputs. Features: - Positive edge-triggere
Stock:10000
Minimum:2
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SOIC
Texas Instruments
Octal D Flip-Flop with 3-STATE Outputs; Package: DIP; No of Pins: 20; Container: Rail
Stock:10000
Minimum:3
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Description: The 74AC74SJ is a dual D-type flip-flop with separate data (D) and clock (CP) inputs. Features: High-speed performance Low power consumption Outputs source/sink 24 mA Inputs
Stock:10000
Minimum:2
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SOIC-20
Texas Instruments
1450+
Octal D Flip-Flop with 3-STATE Outputs; Package: DIP; No of Pins: 20; Container: Rail
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DIP-20
Fsc/ns
02+
Quad 2-Input NAND Gate; Package: SOP; No of Pins: 14; Container: Tape & Reel
Description: The DM74LS273N is a 20-pin dual J-K flip-flop with reset. Features: High-Speed Operation Low Power Consumption TTL Compatible Inputs and Outputs Direct Clear Input Outputs Source/Si
Stock:10000
Minimum:2
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DIP-16
Texas Instruments
DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET
Description: Dual JK Flip-Flop Features: Positive-Edge Triggering Outputs Source/Sink 24 mA Outputs Can Be Used as Inputs to Other Gates Latch-Up Performance Exceeds 250 mA Per JESD 78, Clas
Stock:10000
Minimum:2
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SOP-20
Texas Instruments
07/
Octal D Flip-Flop with 3-STATE Outputs; Package: DIP; No of Pins: 20; Container: Rail
Stock:10000
Minimum:2
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