AD7711ANZ

24 Bits, No Missing Codes 0.0015% Nonlinearity 2-Channel Programmable Gain Front End Gains from 128 1 Differential Input 1 Single-Ended Input Low-Pass Filter with Programmable Filter Cutoffs Ability to Read/Write Calibration Coefficients RTD Excitation Current Sources Bidirectional Microcontroller Serial Interface Internal/External Reference Option Single- or Dual-Supply Operation Low Power (25 mW typ) with Power-Down Mode (7 mW typ)

APPLICATIONS RTD Transducers Process Control Smart Transmitters Portable Industrial Instruments

GENERAL DESCRIPTION The is a complete analog front end for low frequency measurement applications. The device accepts low level signals directly from a transducer and outputs a serial digital word. It employs a - conversion technique to realize to 24 bits of no missing codes performance. The input signal is applied to a proprietary programmable gain front end based around an analog modulator. The modulator output is processed by an on-chip digital filter. The first notch of this digital filter can be programmed via the on-chip control register, allowing adjustment of the filter cutoff and settling time.

The part features one differential analog input and one singleended analog input as well as a differential reference input. Normally, one of the input channels will be used as the main channel with the second channel used as an auxiliary input to periodically measure a second voltage. It can be operated from a single supply (by tying the VSS pin to AGND), provided that the input signals on the analog inputs are more positive than ­30 mV. By taking the VSS pin negative, the part can convert signals down to ­VREF on its inputs. The part provides two current sources that can be used to provide excitation in 3-wire and 4-wire RTD configurations. The AD7711 thus performs all signal conditioning and conversion for a single- or dual-channel system.

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AGND DGND VSS RFS TFS MODE SDATA SCLK DRDY A0

The AD7711 is ideal for use in smart, microcontroller based systems. Gain settings, signal polarity, input channel selection, and RTD current control can be configured in software using the bidirectional serial port. The AD7711 contains selfcalibration, system calibration, and background calibration options, and also allows the user to read and write the on-chip calibration registers.

CMOS construction ensures low power dissipation, and a software programmable power-down mode reduces the standby power consumption to only 7 mW typical. The part is available 24-lead, 0.3-inch-wide, plastic and hermetic dual-in-line package (DIP) as well a 24-lead small outline (SOIC) package.

PRODUCT HIGHLIGHTS 1. The programmable gain front end allows the AD7711 to

accept input signals directly from an RTD transducer, removing a considerable amount of signal conditioning. On-chip current sources provide excitation for 3-wire and 4-wire RTD configurations.

2. No missing codes ensure true, usable, 23-bit dynamic range coupled with excellent ± 0.0015% accuracy. The effects of temperature drift are eliminated by on-chip self-calibration, which removes zero-scale and full-scale errors.

3. The AD7711 is ideal for microcontroller or DSP processor applications with an on-chip control register that allows control over filter cutoff, input gain, channel selection, signal polarity, RTD current control, and calibration modes.

4. The AD7711 allows the user to read and to write the on-chip calibration registers. This means that the microcontroller has much greater control over the calibration procedure.

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+2.5 V; REF IN(­) = AGND; MCLK = 10 MHz unless otherwise stated. All specifications TMIN to TMAX, unless otherwise noted.)

ANALOG INPUTS/REFERENCE INPUTS Normal Mode Hz Rejection6 Normal Mode Rejection6 DC Input Leakage Current @ 25C6 TMIN to TMAX Sampling AIN1/REF IN Common-Mode Rejection (CMR) Common-Mode Rejection (CMR) Common-Mode Hz Rejection6 Common-Mode Hz Rejection6 Common-Mode Voltage Range7 Analog Inputs8 Input Voltage Range9

Input Sampling Rate, fS AIN2 Offset Error AIN2 Offset Drift Reference Inputs REF IN(+) ­ REF IN(­) Voltage11

Output Voltage Initial Tolerance @ 25C Drift Output Noise Line Regulation (AVDD) Load Regulation External Current

Guaranteed by Design. For Filter Notches 60 Hz For Filter Notch 100 Hz For Filter Notch 250 Hz For Filter Notch 500 Hz For Filter Notch = 1 kHz Depends on Filter Cutoffs and Selected Gain Filter Notches 60 Hz Typically ± 0.0003% Excluding Reference Excluding Reference. For Gains 1, 2 Excluding Reference. For Gains of

Excluding Reference Typically ± 0.0006% Excluding Reference. For Gains 1, 2 Excluding Reference. For Gains of

For Filter Notches of 10 Hz, 25 Hz, 50 Hz, 0.02 ¥ fNOTCH For Filter Notches of 10 Hz, 30 Hz, 60 Hz, 0.02 ¥ fNOTCH

At DC and AVDD At DC and AVDD 10 V For Filter Notches of 10 Hz, 25 Hz, 50 Hz, ±0.02 ¥ fNOTCH For Filter Notches of 10 Hz, 30 Hz, 60 Hz, ±0.02 ¥ fNOTCH

For Normal Operation. Depends on Gain Selected Unipolar Input Range (B/U Bit of Control Register = 1) Bipolar Input Range (B/U Bit of Control Register = 0)

For Specified Performance. Part Is Functional with Lower VREF Voltages

NOTES 1Temperature range is as follows: A Version +85C; S Version to +125C. See also Note 16. 2Applies after calibration at the temperature of interest. 3Positive full-scale error applies to both unipolar and bipolar input ranges. 4These errors will be of the order of the output noise of the part, as shown in Table I, after system calibration. These errors will 20 mV typical after self-calibration or background calibration. 5Recalibration at any temperature or use of the background calibration mode will remove these drift errors. 6These numbers are guaranteed by design and/or characterization. 7This common-mode voltage range is allowed, provided the input voltage on AIN(+) and AIN(­) does not exceed AVDD 30 mV and VSS ­ 30 mV. 8The analog inputs present a very high impedance dynamic load that varies with clock frequency and input sample rate. The maximum recommended source resis-

tance depends on the selected gain (see Tables IV and V). 9The analog input voltage range on the AIN1(+) input is given here with respect to the voltage on the AIN1(­) input. The input voltage range on the AIN2 input is

with respect to AGND. The absolute voltage on the analog inputs should not go more positive than AVDD + 30 mV, or more negative than VSS ­ 30 mV. 10VREF = REF IN(+) ­ REF IN(­). 11The reference input voltage range may be restricted by the input voltage range requirement on the VBIAS input.

VINL, Input Low Voltage VINH, Input High Voltage MCLK IN Only VINL, Input Low Voltage VINH, Input High Voltage LOGIC OUTPUTS VOL, Output Low Voltage VOH, Output High Voltage Floating State Leakage Current Floating State Output Capacitance13

See VBIAS Input Section Whichever Is Smaller; V/0 V Nominal AVDD/VSS Whichever Is Smaller; V/0 V Nominal AVDD/VSS See VBIAS Input Section Whichever Is Greater; V/0 V Nominal AVDD/VSS Whichever Is Greater; V/0 V Nominal AVDD/VSS Increasing with Gain

TRANSDUCER BURNOUT Current Initial Tolerance @ 25C Drift

RTD EXCITATION CURRENTS (RTD1, RTD2) Output Current Initial Tolerance @ 25C Drift Initial Matching @ 25C Drift Matching Line Regulation (AVDD) Load Regulation Output Compliance

SYSTEM CALIBRATION Positive Full-Scale Calibration Limit14 Negative Full-Scale Calibration Limit14 Offset Calibration Limit15 Input Span15

Matching between RTD1 and RTD2 Currents Matching between RTD1 and RTD2 Current Drift AVDD 5 V

GAIN Is the Selected PGA Gain (between 1 and 128) GAIN Is the Selected PGA Gain (between 1 and 128) GAIN Is the Selected PGA Gain (between 1 and 128) GAIN Is the Selected PGA Gain (between 1 and 128) GAIN Is the Selected PGA Gain (between 1 and 128)

NOTES AD7711 is tested with the following VBIAS voltages. With AVDD 5 V and VSS 0 V, VBIAS 2.5 V; with AVDD 10 V and VSS 0 V, VBIAS 5 V, and

with AVDD 5 V and VSS ­5 V, VBIAS 13Guaranteed by design, not production tested. 14After calibration, if the analog input exceeds positive full scale, the converter outputs all 1s. If the analog input is less than negative full scale, the device outputs all 0s. 15These calibration and span limits apply, provided the absolute voltage on the analog inputs does not exceed AVDD or go more negative than VSS ­ 30 mV.

The offset calibration limit applies to both the unipolar zero point and the bipolar zero point.