FAN3224T

Description The FAN3223-25 family of dual 4 A gate drivers is designed to

drive N-channel enhancement-mode MOSFETs in low-side switching applications by providing high peak current pulses during the short switching intervals. The driver is available with either TTL or CMOS input thresholds. Internal circuitry provides an under-voltage lockout function by holding the output LOW until the supply voltage is within the operating range. In addition, the drivers feature matched internal propagation delays between A and B channels for applications requiring dual gate drives with critical timing, such as synchronous rectifiers. This also enables connecting two drivers in parallel to effectively double the current capability driving a single MOSFET.

The FAN322X drivers incorporate MillerDriveTM architecture for the final output stage. This bipolar-MOSFET combination provides high current during the Miller plateau stage of the MOSFET turn-on / turn-off process to minimize switching loss, while providing rail-to-rail voltage swing and reverse current capability.

The FAN3223 offers two inverting drivers and the FAN3224 offers two non-inverting drivers. Each device has dual independent enable pins that default ON if not connected. In the FAN3225, each channel has dual inputs of opposite polarity, which allows configuration as non-inverting or inverting with an optional enable function using the second input. If one or both inputs are left unconnected, internal resistors bias the inputs such that the output is pulled LOW to hold the power MOSFET OFF.

Features

Industry-Standard Pinouts 18 V Operating Range 5 A Peak Sink/Source at VDD 4.3 A Sink 2.8 A Source at VOUT 6 V Choice of TTL or CMOS Input Thresholds Three Versions of Dual Independent Drivers:

Dual Inverting + Enable (FAN3223) Dual Non-Inverting + Enable (FAN3224) Dual-Inputs (FAN3225)

Internal Resistors Turn Driver Off If No Inputs MillerDrive Technology 9 ns Typical Rise/Fall Times (2.2 nF Load) Under 20 ns Typical Propagation Delay Matched within ns to the

Double Current Capability by Paralleling Channels 3x3 mm MLP, 8-Lead SOIC Package Rated from to +125°C Ambient These are Pb-Free Devices

*This information is generic. Please refer to device data sheet for actual part marking. Pb-Free indicator, "G" or microdot " G", may or may not be present.

See detailed ordering and shipping information on page 20 of this data sheet.
Applications

Switch-Mode Power Supplies High-Efficiency MOSFET Switching Synchronous Rectifier Circuits DC-to-DC Converters Motor Control

1. Estimates derived from thermal simulation; actual values depend on the application. 2. Theta_JL (QJL): Thermal resistance between the semiconductor junction and the bottom surface of all the leads (including any thermal pad)

that are typically soldered to a PCB. 3. Theta_JT (QJT): Thermal resistance between the semiconductor junction and the top surface of the package, assuming it is held at a uniform

temperature by a top-side heatsink. 4. Theta_JA (QJA): Thermal resistance between junction and ambient, dependent on the PCB design, heat sinking, and airflow. The value given

is for natural convection with no heatsink using a 2S2P board, as specified in JEDEC standards JESD51-2, JESD51-5, and JESD51-7, as appropriate. 5. Psi_JB (YJB): Thermal characterization parameter providing correlation between semiconductor junction temperature and an application circuit board reference point for the thermal environment defined in Note 4. For the MLP-8 package, the board reference is defined as the PCB copper connected to the thermal pad and protruding from either end of the package. For the SOIC-8 package, the board reference is defined as the PCB copper adjacent to pin 6. Psi_JT (YJT): Thermal characterization parameter providing correlation between the semiconductor junction temperature and the center of the top of the package for the thermal environment defined in Note 4.

GND INA INA+ INA- INB INB+ INB- OUTA OUTB OUTA

Pin Description Enable Input for Channel A. Pull pin LOW to inhibit driver A. ENA has TTL thresholds for both TTL and CMOS INx threshold

Enable Input for Channel B. Pull pin LOW to inhibit driver B. ENB has TTL thresholds for both TTL and CMOS INx threshold

Ground. Common ground reference for input and output circuits Input to Channel A Non-Inverting Input to Channel A. Connect to VDD to enable output Inverting Input to Channel A. Connect to GND to enable output Input to Channel B Non-Inverting Input to Channel B. Connect to VDD to enable output Inverting Input to Channel B. Connect to GND to enable output Gate Drive Output A: Held LOW unless required input(s) are present and VDD is above UVLO threshold Gate Drive Output B: Held LOW unless required input(s) are present and VDD is above UVLO threshold Gate Drive Output A (inverted from the input): Held LOW unless required input is present and VDD is above UVLO threshold

Gate Drive Output B (inverted from the input): Held LOW unless required input is present and VDD is above UVLO threshold

Thermal Pad (MLP only). Exposed metal on the bottom of the package; may be left floating or connected to GND; NOT suitable for carrying current

7. Default input signal if no external connection is made.