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DS90CR215MTD The DS90CR215 transmitter converts 21 bits of CMOS/TTL data into three LVDS (Low Voltage Differential Signaling) data streams. A phase-locked transmit clock is transmitted in parallel with the data streams over a fourth LVDS link. Every cycle of the transmit clock 21 bits of input data are sampled and transmitted. The DS90CR216 receiver converts the LVDS data streams back into 21 bits of CMOS/TTL data. At a transmit clock frequency of 66 MHz, 21 bits of TTL data are transmitted at a rate of 462 Mbps per LVDS data channel. Using a 66 MHz clock, the data throughput is 1.386 Gbit/s (173 Mbytes/s).
The multiplexing of the data lines provides a substantial cable reduction. Long distance parallel single-ended buses typically require a ground wire per active signal (and have very limited noise rejection capability). Thus, for a 21-bit wide data and one clock, up to 44 conductors are required. With the Channel Link chipset as few as 9 conductors (3 data pairs, 1 clock pair and a minimum of one ground) are needed. This provides a 80% reduction in required cable width, which provides a system cost savings, reduces connector physical size and cost, and reduces shielding requirements due to the cables' smaller form factor.
The 21 CMOS/TTL inputs can support a variety of signal combinations. For example, five 4-bit nibbles plus 1 control, or two 9-bit (byte + parity) and 3 control.
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Description

The DS90CR215 transmitter converts 21 bits of CMOS/TTL data into three LVDS (Low Voltage Differential Signaling) data streams. A phase-locked transmit clock is transmitted in parallel with the data streams over a fourth LVDS link. Every cycle of the transmit clock 21 bits of input data are sampled and transmitted. The DS90CR216 receiver converts the LVDS data streams back into 21 bits of CMOS/TTL data. At a transmit clock frequency of 66 MHz, 21 bits of TTL data are transmitted at a rate of 462 Mbps per LVDS data channel. Using a 66 MHz clock, the data throughput is 1.386 Gbit/s (173 Mbytes/s). The multiplexing of the data lines provides a substantial cable reduction. Long distance parallel single-ended buses typically require a ground wire per active signal (and have very limited noise rejection capability). Thus, for a 21-bit wide data and one clock, up to 44 conductors are required. With the Channel Link chipset as few as 9 conductors (3 data pairs, 1 clock pair and a minimum of one ground) are needed. This provides a 80% reduction in required cable width, which provides a system cost savings, reduces connector physical size and cost, and reduces shielding requirements due to the cables' smaller form factor. The 21 CMOS/TTL inputs can support a variety of signal combinations. For example, five 4-bit nibbles plus 1 control, or two 9-bit (byte + parity) and 3 control.

Not found, similar datasheet recommended

Title

+3.3V Rising Edge Data Strobe LVDS 21-Bit Channel Link Transmitter - 66 MHz

  • ECAD Module
  • Transmission Data Rate: 173.25(MBps)
  • Brand: National Semiconductor
  • DateCode: 03
  • Package / Case: TSSOP-48
  • Differential Input High Threshold Voltage: 0.1(mV)
  • Power Dissipation: 1980(W)
  • Mounting: Surface Mount
  • Differential Output Voltage: 0.45(mV)
  • Operating Temp Range: -40C to 85C
  • Package Type: TSSOP
  • Packaging: Rail/Tube
  • Pin Count: 48
  • Operating Temperature (Max): 85C
  • Operating Temperature (Min): -40C
  • Number of Elements: 3
  • Input Type: CMOS/TTL
  • Number of Drivers: 3
  • Number of Receivers: 21
  • Operating Temperature Classification: Industrial
  • Diff. Input Low Threshold Volt: -0.1(mV)
  • Rad Hardened: No
  • Operating Supply Voltage (Typ): 3.3(V)

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ECAD Module

Product Attributes

  • Description: Dual FPD-Link III Deserializer Features: - Low power consumption - High speed serializer/deserializer - Supports up to 1.5 Gbps data rate - Supports up to 4 lanes of data - Supports up to 1080p60 video - Supports up to 3.3V I/O - Supports LVDS output Application: The DS90CR215MTD is a dual FPD-Link III deserializer designed for automotive infotainment systems. It is used to convert high speed serial data to low voltage differential signaling (LVDS) for display applications. It is ideal for applications such as rear seat entertainment, navigation systems and instrument clusters. (For reference only)

Preview of the first 3 pages of the data sheet

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DS90CR215/DS90CR216 +3.3V Rising Edge Data Strobe LVDS 21-Bit Channel Link - 66 MHz
FEATURES

mW (typ) Power-down Mode (<0.5 mW total) to 173 Megabytes/sec Bandwidth to 1.386 Gbps Data Throughput Narrow Bus Reduces Cable Size 290 mV Swing LVDS Devices for Low EMI +1V Common Mode Range (Around +1.2V) PLL Requires No External Components Low Profile 48-Lead TSSOP Package Rising Edge Data Strobe Compatible with TIA/EIA-644 LVDS Standard ESD Rating > 7 kV Operating Temperature: to +85°C

DESCRIPTION

The DS90CR215 transmitter converts 21 bits of CMOS/TTL data into three LVDS (Low Voltage Differential Signaling) data streams. A phase-locked transmit clock is transmitted in parallel with the data streams over a fourth LVDS link. Every cycle of the transmit clock 21 bits of input data are sampled and transmitted. The DS90CR216 receiver converts the LVDS data streams back into 21 bits of CMOS/TTL data. At a transmit clock frequency of 66 MHz, 21 bits of TTL data are transmitted at a rate of 462 Mbps per LVDS data channel. Using a 66 MHz clock, the data throughput is 1.386 Gbit/s (173 Mbytes/s).

The multiplexing of the data lines provides a substantial cable reduction. Long distance parallel single-ended buses typically require a ground wire per active signal (and have very limited noise rejection capability). Thus, for a 21-bit wide data and one clock, to 44 conductors are required. With the Channel Link chipset as few as 9 conductors (3 data pairs, 1 clock pair and a minimum of one ground) are needed. This provides a 80% reduction in required cable width, which provides a system cost savings, reduces connector physical size and cost, and reduces shielding requirements due to the cables' smaller form factor.

The 21 CMOS/TTL inputs can support a variety of signal combinations. For example, five 4-bit nibbles plus 1 control, or two 9-bit (byte + parity) and 3 control.

Figure DS90CR216 - Improved AC Specifications See Package Number DGG0048A Recommended Alternative Device

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.

Supply Voltage (VCC) CMOS/TTL Input Voltage CMOS/TTL Output Voltage LVDS Receiver Input Voltage LVDS Driver Output Voltage LVDS Output Short Circuit Duration Junction Temperature Storage Temperature Range Lead Temperature (Soldering, 4 sec.) Maximum Package Power Dissipation @ +25°C

(1) If Military/Aerospace specified devices are required, please contact the TI Sales Office/ Distributors for availability and specifications. (2) "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. They are not meant to

imply that the device should be operated at these limits. "Electrical Characteristics" specify conditions for device operation.

Supply Voltage (VCC) Operating Free Air Temperature (TA) Receiver Input Range Supply Noise Voltage (VCC)

Over recommended operating supply and temperature ranges unless otherwise specified
Change V OD between Complimentary Output States Offset Voltage(1)
(1) VOS previously referred as VCM. Copyright © 1999­2013, Texas Instruments Incorporated

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    6 buyer reviews from Philippines

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    Kim Benedict Chua

    UDN2559B
    ph Philippines Manila

    Length of registration:3 years

    Got it in very good packaging. Will test and hopefully it will work well. Thank you!

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    03/17/2021

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    Ramon R. Reyes

    2SC2904
    ph Philippines Marikina City

    Length of registration:12 years

    works good! fm DU1FV

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    03/27/2017

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    Norman Tayo

    FGH60N60
    ph Philippines ILOILO CITY

    Length of registration:10 years

    THANK YOU...GOT THE ITEM QUICKLY.

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    02/06/2017

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    • DS90CR215MTD The DS90CR215 transmitter converts 21 bits of CMOS/TTL data into three LVDS (Low Voltage Differential Signaling) data streams. A phase-locked transmit clock is transmitted in parallel with the data streams over a fourth LVDS link. Every cycle of the transmit clock 21 bits of input data are sampled and transmitted. The DS90CR216 receiver converts the LVDS data streams back into 21 bits of CMOS/TTL data. At a transmit clock frequency of 66 MHz, 21 bits of TTL data are transmitted at a rate of 462 Mbps per LVDS data channel. Using a 66 MHz clock, the data throughput is 1.386 Gbit/s (173 Mbytes/s). The multiplexing of the data lines provides a substantial cable reduction. Long distance parallel single-ended buses typically require a ground wire per active signal (and have very limited noise rejection capability). Thus, for a 21-bit wide data and one clock, up to 44 conductors are required. With the Channel Link chipset as few as 9 conductors (3 data pairs, 1 clock pair and a minimum of one ground) are needed. This provides a 80% reduction in required cable width, which provides a system cost savings, reduces connector physical size and cost, and reduces shielding requirements due to the cables' smaller form factor. The 21 CMOS/TTL inputs can support a variety of signal combinations. For example, five 4-bit nibbles plus 1 control, or two 9-bit (byte + parity) and 3 control.
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