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Главная страница > Электронные Компоненты > Интегральные микросхемы > Интерфейс - Специальные интерфейсы
TSSOP-48
National Semiconductor
03
The DS90CR215 transmitter converts 21 bits of CMOS/TTL data into three LVDS (Low Voltage Differential Signaling) data streams. A phase-locked transmit clock is transmitted in parallel with the data streams over a fourth LVDS link. Every cycle of the transmit clock 21 bits of input data are sampled and transmitted. The DS90CR216 receiver converts the LVDS data streams back into 21 bits of CMOS/TTL data. At a transmit clock frequency of 66 MHz, 21 bits of TTL data are transmitted at a rate of 462 Mbps per LVDS data channel. Using a 66 MHz clock, the data throughput is 1.386 Gbit/s (173 Mbytes/s). The multiplexing of the data lines provides a substantial cable reduction. Long distance parallel single-ended buses typically require a ground wire per active signal (and have very limited noise rejection capability). Thus, for a 21-bit wide data and one clock, up to 44 conductors are required. With the Channel Link chipset as few as 9 conductors (3 data pairs, 1 clock pair and a minimum of one ground) are needed. This provides a 80% reduction in required cable width, which provides a system cost savings, reduces connector physical size and cost, and reduces shielding requirements due to the cables' smaller form factor. The 21 CMOS/TTL inputs can support a variety of signal combinations. For example, five 4-bit nibbles plus 1 control, or two 9-bit (byte + parity) and 3 control.
Description: Dual FPD-Link III Deserializer Features: - Low power consumption - High speed serializer/deserializer - Supports up to 1.5 Gbps data rate - Supports up to 4 lanes of data - Supports up t
Наличность:10000
Минимальное количество заказа:1
В избранное
DIP-28
Har/isl
03+
The Intersil 82C59A is a high performance CMOS Priority Interrupt Controller manufactured using an advanced 2μm CMOS process. The 82C59A is designed to relieve the system CPU from the task of polling in a multilevel priority system. The high speed and industry standard configuration of the 82C59A make it compatible with microprocessors such as 80C286, 80286, 80C86/88, 8086/88, 8080/85 and NSC800. The 82C59A can handle up to eight vectored priority interrupting sources and is cascadable to 64 without additional circuitry. Individual interrupting sources can be masked or prioritized to allow custom system configuration. Two modes of operation make the 82C59A compatible with both 8080/85 and 80C86/88/286 formats. Static CMOS circuit design ensures low operating power. The Intersil advanced CMOS process results in performance equal to or greater than existing equivalent products at a fraction of the power.
The CP82C59A is a 28-pin DIP integrated circuit (IC) manufactured by Intersil. It is a programmable peripheral interface (PPI) chip designed for use in the IBM PC/AT and compatible computers. It is an
Наличность:10000
Минимальное количество заказа:2
В избранное
PLCC44
Zilog
Core / Cpu Used = Z80 ;; External Memory = -- ;; Speed = 6, 8, 10 ;; I/O = 16 ;; Timers = no ;; Communications Controller = Pio ;; Other Features = Two 8-bit Ports ;;
Description: Z84C2010VEC is a Zilog Z80 microprocessor with a 44-pin PLCC package. Features: 8-bit microprocessor Operating frequency up to 8 MHz On-chip clock generator On-chip ROM and RAM On-ch
Наличность:5000
Минимальное количество заказа:1
В избранное
The Z85C3008VSC is a Zilog 8-bit microcontroller with a PLCC-44 package. It is a member of the Z8 microcontroller family and is designed for use in embedded control applications. Features: * 8-bit CP
Наличность:10000
Минимальное количество заказа:1
В избранное
The Z84C4008PEC is a Zilog Z80 microprocessor that is designed to be used in embedded systems. It is a 40-pin DIP package and operates at a maximum frequency of 8MHz. It has an 8-bit data bus and a 16
Наличность:10000
Минимальное количество заказа:1
В избранное
DIP
Zilog
10+
The DS90CR215 transmitter converts 21 bits of CMOS/TTL data into three LVDS (Low Voltage Differential Signaling) data streams. A phase-locked transmit clock is transmitted in parallel with the data streams over a fourth LVDS link. Every cycle of the transmit clock 21 bits of input data are sampled and transmitted. The DS90CR216 receiver converts the LVDS data streams back into 21 bits of CMOS/TTL data. At a transmit clock frequency of 66 MHz, 21 bits of TTL data are transmitted at a rate of 462 Mbps per LVDS data channel. Using a 66 MHz clock, the data throughput is 1.386 Gbit/s (173 Mbytes/s). The multiplexing of the data lines provides a substantial cable reduction. Long distance parallel single-ended buses typically require a ground wire per active signal (and have very limited noise rejection capability). Thus, for a 21-bit wide data and one clock, up to 44 conductors are required. With the Channel Link chipset as few as 9 conductors (3 data pairs, 1 clock pair and a minimum of one ground) are needed. This provides a 80% reduction in required cable width, which provides a system cost savings, reduces connector physical size and cost, and reduces shielding requirements due to the cables' smaller form factor. The 21 CMOS/TTL inputs can support a variety of signal combinations. For example, five 4-bit nibbles plus 1 control, or two 9-bit (byte + parity) and 3 control.
Description: The Z84C4208PEC is a Z80 microprocessor from Zilog, Inc. It is a 8-bit microprocessor with an 8-bit data bus and a 16-bit address bus. Features: 8-bit microprocessor 8-bit data bus 1
Наличность:10000
Минимальное количество заказа:1
В избранное
PLCC44
Zilog
10+
The DS90CR215 transmitter converts 21 bits of CMOS/TTL data into three LVDS (Low Voltage Differential Signaling) data streams. A phase-locked transmit clock is transmitted in parallel with the data streams over a fourth LVDS link. Every cycle of the transmit clock 21 bits of input data are sampled and transmitted. The DS90CR216 receiver converts the LVDS data streams back into 21 bits of CMOS/TTL data. At a transmit clock frequency of 66 MHz, 21 bits of TTL data are transmitted at a rate of 462 Mbps per LVDS data channel. Using a 66 MHz clock, the data throughput is 1.386 Gbit/s (173 Mbytes/s). The multiplexing of the data lines provides a substantial cable reduction. Long distance parallel single-ended buses typically require a ground wire per active signal (and have very limited noise rejection capability). Thus, for a 21-bit wide data and one clock, up to 44 conductors are required. With the Channel Link chipset as few as 9 conductors (3 data pairs, 1 clock pair and a minimum of one ground) are needed. This provides a 80% reduction in required cable width, which provides a system cost savings, reduces connector physical size and cost, and reduces shielding requirements due to the cables' smaller form factor. The 21 CMOS/TTL inputs can support a variety of signal combinations. For example, five 4-bit nibbles plus 1 control, or two 9-bit (byte + parity) and 3 control.
Наличность:10000
Минимальное количество заказа:1
В избранное
PLCC44
Zilog
10+
The DS90CR215 transmitter converts 21 bits of CMOS/TTL data into three LVDS (Low Voltage Differential Signaling) data streams. A phase-locked transmit clock is transmitted in parallel with the data streams over a fourth LVDS link. Every cycle of the transmit clock 21 bits of input data are sampled and transmitted. The DS90CR216 receiver converts the LVDS data streams back into 21 bits of CMOS/TTL data. At a transmit clock frequency of 66 MHz, 21 bits of TTL data are transmitted at a rate of 462 Mbps per LVDS data channel. Using a 66 MHz clock, the data throughput is 1.386 Gbit/s (173 Mbytes/s). The multiplexing of the data lines provides a substantial cable reduction. Long distance parallel single-ended buses typically require a ground wire per active signal (and have very limited noise rejection capability). Thus, for a 21-bit wide data and one clock, up to 44 conductors are required. With the Channel Link chipset as few as 9 conductors (3 data pairs, 1 clock pair and a minimum of one ground) are needed. This provides a 80% reduction in required cable width, which provides a system cost savings, reduces connector physical size and cost, and reduces shielding requirements due to the cables' smaller form factor. The 21 CMOS/TTL inputs can support a variety of signal combinations. For example, five 4-bit nibbles plus 1 control, or two 9-bit (byte + parity) and 3 control.
Description: Z84C1008VEC is a Zilog Z80 microprocessor in a 44-pin PLCC package. Features: 8-bit CPU Clock frequency up to 8MHz On-chip ROM and RAM Interrupt controller Serial port I/O port Tim
Наличность:10000
Минимальное количество заказа:1
В избранное
Наличность:5000
Минимальное количество заказа:1
В избранное
SOP-16
PHL
06
4-Channel I2C And SMBus Multiplexer With Reset Functions 16-SOIC -40 to 85
Наличность:10000
Минимальное количество заказа:1
В избранное
The HCTL-1100 is a 40-pin DIP (dual in-line package) integrated circuit (IC) manufactured by Hewlett Packard (HP). It is a high-performance, single-chip, quadrature encoder interface. It is designed t
Наличность:2000
Минимальное количество заказа:1
В избранное
DIP40
Zilog
9328+
The DS90CR215 transmitter converts 21 bits of CMOS/TTL data into three LVDS (Low Voltage Differential Signaling) data streams. A phase-locked transmit clock is transmitted in parallel with the data streams over a fourth LVDS link. Every cycle of the transmit clock 21 bits of input data are sampled and transmitted. The DS90CR216 receiver converts the LVDS data streams back into 21 bits of CMOS/TTL data. At a transmit clock frequency of 66 MHz, 21 bits of TTL data are transmitted at a rate of 462 Mbps per LVDS data channel. Using a 66 MHz clock, the data throughput is 1.386 Gbit/s (173 Mbytes/s). The multiplexing of the data lines provides a substantial cable reduction. Long distance parallel single-ended buses typically require a ground wire per active signal (and have very limited noise rejection capability). Thus, for a 21-bit wide data and one clock, up to 44 conductors are required. With the Channel Link chipset as few as 9 conductors (3 data pairs, 1 clock pair and a minimum of one ground) are needed. This provides a 80% reduction in required cable width, which provides a system cost savings, reduces connector physical size and cost, and reduces shielding requirements due to the cables' smaller form factor. The 21 CMOS/TTL inputs can support a variety of signal combinations. For example, five 4-bit nibbles plus 1 control, or two 9-bit (byte + parity) and 3 control.
Наличность:5000
Минимальное количество заказа:1
В избранное
SOP24
STMicroelectronics
11+
The DS90CR215 transmitter converts 21 bits of CMOS/TTL data into three LVDS (Low Voltage Differential Signaling) data streams. A phase-locked transmit clock is transmitted in parallel with the data streams over a fourth LVDS link. Every cycle of the transmit clock 21 bits of input data are sampled and transmitted. The DS90CR216 receiver converts the LVDS data streams back into 21 bits of CMOS/TTL data. At a transmit clock frequency of 66 MHz, 21 bits of TTL data are transmitted at a rate of 462 Mbps per LVDS data channel. Using a 66 MHz clock, the data throughput is 1.386 Gbit/s (173 Mbytes/s). The multiplexing of the data lines provides a substantial cable reduction. Long distance parallel single-ended buses typically require a ground wire per active signal (and have very limited noise rejection capability). Thus, for a 21-bit wide data and one clock, up to 44 conductors are required. With the Channel Link chipset as few as 9 conductors (3 data pairs, 1 clock pair and a minimum of one ground) are needed. This provides a 80% reduction in required cable width, which provides a system cost savings, reduces connector physical size and cost, and reduces shielding requirements due to the cables' smaller form factor. The 21 CMOS/TTL inputs can support a variety of signal combinations. For example, five 4-bit nibbles plus 1 control, or two 9-bit (byte + parity) and 3 control.
Description: LED Driver IC, Step-Down, 1.2MHz, 16V, 3A, SOP-24 Features: High Efficiency up to 95% 1.2MHz Fixed Frequency Operation Low Ripple Burst Mode Operation Low Quiescent Current Internal
Наличность:10000
Минимальное количество заказа:10
В избранное
Наличность:5000
Минимальное количество заказа:1
В избранное
The ZPSD302B-70J is a PLCC-44 (Plastic Leaded Chip Carrier) integrated circuit manufactured by Zilog. It is a 16-bit microcontroller with a Z80 CPU core. It has a maximum clock speed of 7 MHz, and is
Наличность:2000
Минимальное количество заказа:1
В избранное
Description: Dual LVDS Receiver Features: - Low power consumption - High speed data rate up to 1.25 Gbps - Low voltage differential signaling (LVDS) - Low EMI/RFI - Small package size - Compatible wit
Наличность:10000
Минимальное количество заказа:1
В избранное
Description: MCZ33989EG is a low-power, low-noise, high-accuracy, low-dropout linear regulator from Freescale Semiconductor. Features: Low dropout voltage of 0.2V Low quiescent current of 1.2mA
Наличность:10000
Минимальное количество заказа:1
В избранное
The DS90CR211MTD is a low-power, low-skew, 1-to-2 differential line receiver designed for high-speed data transmission applications. It is designed to meet the requirements of the PCI Express, Serial
Наличность:10000
Минимальное количество заказа:1
В избранное
Наличность:5000
Минимальное количество заказа:1
В избранное
Description: Z0853008PSC is a microcontroller designed by Zilog, built using MOS silicon gate technology, and packaged in a 40-pin DIP (Dual In-line Package). Features: This chip is capable of proce
Наличность:10000
Минимальное количество заказа:1
В избранное
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