AD7730LBRZ

KEY FEATURES Resolution of 230,000 Counts (Peak-to-Peak) Offset Drift: 5 nV/C Gain Drift: 2 ppm/C Line Frequency Rejection: >150 dB Buffered Differential Inputs Programmable Filter Cutoffs Specified for Drift Over Time Operates with Reference Voltages 5 V

ADDITIONAL FEATURES Two-Channel Programmable Gain Front End On-Chip DAC for Offset/TARE Removal FASTStepTM Mode or DC Excitation Single Supply Operation

GENERAL DESCRIPTION The is a complete analog front end for weigh-scale and pressure measurement applications. The device accepts lowlevel signals directly from a transducer and outputs a serial digital word. The input signal is applied to a proprietary programmable gain front end based around an analog modulator.

The modulator output is processed by a low pass programmable digital filter, allowing adjustment of filter cutoff, output rate and settling time.

The part features two buffered differential programmable gain analog inputs as well as a differential reference input. The part operates from a single +5 V supply. It accepts four unipolar analog input ranges: to +10 mV, +20 mV, +40 mV and +80 mV and four bipolar ranges: ± 10 mV, ± 20 mV, 40 mV and ± 80 mV. The peak-to-peak resolution achievable directly from the part in 230,000 counts. An on-chip 6-bit DAC allows the removal of TARE voltages. Clock signals for synchronizing ac excitation of the bridge are also provided.

The serial interface on the part can be configured for three-wire operation and is compatible with microcontrollers and digital signal processors. The AD7730 contains self-calibration and system calibration options, and features an offset drift of less than 5 nV/°C and a gain drift of less than 2 ppm/°C.

The AD7730 is available a 24-pin plastic DIP, a 24-lead SOIC and 24-lead TSSOP package. The AD7730L is available a 24-lead SOIC and 24-lead TSSOP package.

NOTE The description of the functions and operation given in this data sheet apply to both the AD7730 and AD7730L. Specifications and performance parameters differ for the parts. Specifications for the AD7730L are outlined in Appendix A.

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

AD7730­SPECIFICATIONS (AVDD +5 V, DVDD +5 V; REF IN(+) = AVDD; REF IN(­) = AGND = DGND 0 V; fCLK = 4.9152 MHz. All specifications TMIN to TMAX unless otherwise noted.)

STATIC PERFORMANCE (CHP 1) No Missing Codes2 Output Noise and Update Rates2

Integral Nonlinearity Offset Error2 Offset Drift vs. Temperature2 Offset Drift vs. Time4 Positive Full-Scale Error2, 5 Positive Full-Scale Drift 6, 7 Positive Full-Scale Drift vs Time4 Gain Error2, 8 Gain Drift vs. 6, 9 Gain Drift vs. Time4 Bipolar Negative Full-Scale Error2 Negative Full-Scale Drift vs. Temp2, 6

Common-Mode Rejection (CMR) Analog Input DC Bias Current2 Analog Input DC Bias Current Drift2 Analog Input DC Offset Current2 Analog Input DC Offset Current Drift2

Offset Error Offset Drift vs. Temperature6 Offset Drift vs. Time4 Positive Full-Scale Error5 Positive Full-Scale Drift vs. Temp6, 7 Positive Full-Scale Drift vs. Time4 Gain Error8 Gain Drift vs. Temperature6, 9 Gain Drift vs. Time4

Reference Input REF IN(+) ­ REF IN(­) Voltage REF IN(+) ­ REF IN(­) Voltage Absolute/Common-Mode Voltage13

Offset Error and Offset Drift Refer to Both Unipolar Offset and Bipolar Zero Errors
Measured with Zero Differential Voltage At DC. Measured with Zero Differential Voltage
SKIP = 010 Offset Error and Offset Drift Refer to Both Unipolar Offset and Bipolar Zero Errors

Measured with Zero Differential Voltage At DC. Measured with Zero Differential Voltage At DC. Measured with Zero Differential Voltage

From 51 Hz From 61 Hz From 51 Hz From 61 Hz Assuming 5 V Reference with HIREF Bit Set Appropriately Gain = 250 Gain = 125 Gain = 62.5 Gain = 31.25

HIREF Bit of Mode Register = 0 HIREF Bit of Mode Register 1 NO REF Bit Active If VREF Below This Voltage NO REF Bit Inactive If VREF Above This Voltage

LOGIC INPUTS Input Current All Inputs Except SCLK and MCLK IN VINL, Input Low Voltage VINL, Input Low Voltage VINH, Input High Voltage SCLK Only (Schmitt Triggered Input) VT+ VT­ VT+ ­ VT­ VT+ ­ VT­ MCLK IN Only VINL, Input Low Voltage VINL, Input Low Voltage VINH, Input High Voltage VINH, Input High Voltage

LOGIC OUTPUTS (Including MCLK OUT) VOL, Output Low Voltage
Floating State Leakage Current Floating State Output Capacitance2
Negative Full-Scale Calibration Limit17 Offset Calibration Limit18 Input Span17

POWER REQUIREMENTS Power Supply Voltages AVDD ­ AGND Voltage DVDD Voltage Power Supply Currents AVDD Current (Normal Mode) AVDD Current (Normal Mode) DVDD Current (Normal Mode) DVDD Current (Normal Mode) AVDD + DVDD Current (Standby Mode) Power Dissipation Normal Mode

DVDD +5 V DVDD +3 V DVDD +5 V DVDD +3 V DVDD +5 V DVDD +3 V DVDD +5 V DVDD +3 V DVDD +5 V DVDD +3 V

ISINK 800 A Except for MCLK +5 V ISINK 100 A Except for MCLK +3 V ISOURCE 200 A Except for MCLK +5 V ISOURCE 100 A Except for MCLK +3 V

With AGND 0 V External MCLK. Digital I/Ps V or DVDD All Input Ranges Except +10 mV and 10 mV Input Ranges +10 mV and 10 mV Only DVDD 3.3 V DVDD 5.25 V Typically 10 A. External MCLK V or DVDD AVDD = DVDD +5 V. Digital I/Ps V or DVDD All Input Ranges Except +10 mV and 10 mV Input Ranges +10 mV and 10 mV Only Typically 50 W. External MCLK V or DVDD