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CD4502BM CD4502B consists of six inverter/buffers with 3-state outputs. A logic "1" on the OUTPUT DISABLE input produces a high-impedance state in all six outputs. This feature permits common busing of the outputs, thus simplifying system design. A Logic "1" on the INHIBIT input switches all six outputs to logic "0" if the OUTPUT DISABLE input is a logic "0". This device is capable of driving two standard TTL loads, which is equivalent to six times the JEDEC "B"-series IOL standard.
The CD4502B types are supplied in 16-lead hermetic dual-in-line ceramic packages (F3A suffix), 16-lead dual-in-line plastic packages (E suffix), 16-lead small-outline packages (NSR suffix), and 16-lead thin shrink small-outline packages (PW and PWR suffixes).
  • CD4502BM
  • CD4502BM
  • CD4502BM
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产品描述

CD4502B consists of six inverter/buffers with 3-state outputs. A logic "1" on the OUTPUT DISABLE input produces a high-impedance state in all six outputs. This feature permits common busing of the outputs, thus simplifying system design. A Logic "1" on the INHIBIT input switches all six outputs to logic "0" if the OUTPUT DISABLE input is a logic "0". This device is capable of driving two standard TTL loads, which is equivalent to six times the JEDEC "B"-series IOL standard. The CD4502B types are supplied in 16-lead hermetic dual-in-line ceramic packages (F3A suffix), 16-lead dual-in-line plastic packages (E suffix), 16-lead small-outline packages (NSR suffix), and 16-lead thin shrink small-outline packages (PW and PWR suffixes).

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标题

CMOS Strobed Hex Inverter/Buffer with 3-State Outputs

  • ECAD Module
  • Logic Family: 4000
  • Brand: Texas Instruments
  • Package / Case: SOP-16
  • Logic Function: Buffer, Driver
  • Number of Channels per Chip: 6
  • Input Type: Single Ended
  • Output Type: 3 State
  • Polarity: Inverting
  • Mounting Type: Surface Mount
  • Package Type: SOIC
  • Pin Count: 16
  • Maximum High Level Output Current: -4.2mA
  • Maximum Low Level Output Current: 25.2mA
  • Maximum Propagation Delay Time @ Maximum CL: 380 ns @ 5 V
  • Dimensions: 9.9 x 3.91 x 1.58mm
  • Height: 1.58mm
  • Minimum Operating Temperature: -55 °C
  • Minimum Operating Supply Voltage: 3 V
  • Width: 3.91mm
  • Maximum Operating Supply Voltage: 18 V
  • Length: 9.9mm
  • Propagation Delay Test Condition: 50pF
  • Maximum Operating Temperature: +125 °C

本网站上使用的所有产品名称,商标,品牌和徽标均为其各自所有者的财产。 具有这些名称,商标,品牌和徽标的产品的描述或销售仅用于标识目的,并不表示与任何权利所有者有任何隶属关系或授权。

ECAD Module

产品属性

数据表前3页预览

  • CD4502BM's pdf picture 1
  • CD4502BM's pdf picture 2
  • CD4502BM's pdf picture 3

文档预览

Data sheet acquired from Harris Semiconductor SCHS067B ­ Revised July 2003

The CD4502B types are supplied in 16-lead hermetic dual-in-line ceramic packages (F3A suffix), 16-lead dual-in-line plastic packages (E suffix), 16-lead small-outline packages (NSR suffix), and 16-lead thin shrink small-outline packages (PW and PWR suffixes).

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Enhanced Product Quadruple Bus Buffer Gates With 3-State Outputs.
SN74AUC2G06
Dual Inverter Buffer/Driver with Open Drain Outputs.
SN74AHC04Q
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CY54FCT244T
Octal Buffers and Line Drivers with 3-State Outputs.
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    • CD4502BM CD4502B consists of six inverter/buffers with 3-state outputs. A logic "1" on the OUTPUT DISABLE input produces a high-impedance state in all six outputs. This feature permits common busing of the outputs, thus simplifying system design. A Logic "1" on the INHIBIT input switches all six outputs to logic "0" if the OUTPUT DISABLE input is a logic "0". This device is capable of driving two standard TTL loads, which is equivalent to six times the JEDEC "B"-series IOL standard. The CD4502B types are supplied in 16-lead hermetic dual-in-line ceramic packages (F3A suffix), 16-lead dual-in-line plastic packages (E suffix), 16-lead small-outline packages (NSR suffix), and 16-lead thin shrink small-outline packages (PW and PWR suffixes).
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      CD4502BM

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