RequiredAT28C256-15PU
类别: 内存
产品描述： 256K 32K x 8 Paged CMOS E2PROM
Price range ($)
4.47040 7.67200
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AT28C256-15PU
AT28C256-15PU has several brands around the world that may have alternate names for AT28C256-15PU due to regional differences or acquisition. AT28C256-15PU may also be known as the following names:
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产品描述
AT28C256-15PU
库存:9999 |
Atmel |
256K 32K x 8 Paged CMOS E2PROM |
≥1: US $7.67200 US $6.90480 ≥5: US $7.28840 US $6.55956 ≥10: US $6.90480 US $6.21432 ≥20: US $6.71300 US $6.04170 ≥50: US $6.52120 US $5.86908 ≥100: US $6.32940 US $5.69646 ≥200: US $6.13760 US $5.52384 ≥500: US $6.06088 US $5.45479 ≥1000: US $5.94580 US $5.35122
更多:
询价
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AT28C256-15PU
库存:478 |
Atmel 13+ |
256K 32K x 8 Paged CMOS E2PROM |
≥1: US $7.54380 US $6.78942
更多:
询价
|
AT28C256-15PU
库存:225 |
AT 15+ |
256K 32K x 8 Paged CMOS E2PROM |
≥1: US $4.47040 US $4.02336
更多:
询价
|
Features
● Fast Read Access Time - 150ns
● Automatic Page Write Operation
- Internal Address and Data Latches for 64 Bytes
- Internal Control Timer
● Fast Write Cycle Times
- Page Write cycle Time: 3 ms or 10 ms Maximum
- 1 to 64-byte Page write Operation
● Low Power Dissipation
- 50mA Active current
- 200μA CMOS Standby current
● Hardware and Software Data Protection
● DATA Polling for End of Write Detection
● High Reliability CMOS Technology
- Endurance: 104 or 105 cycles
- Data Retention: 10 Years
● Single 5V ±10% Supply
● CMOS and TTL compatible Inputs and Outputs
● JEDEC Approved Byte-wide Pinout
● Full Military and Industrial Temperature Ranges
● Green (Pb/Halide-free) Packaging Option
Description
The AT28C256 is a high-performance electrically erasable and programmable read-only memory. Its 256K of memory is organized as 32,768 words by 8 bits. Manufactured with Atmel's advanced nonvolatile CMOS technology, the device offers access times to 150ns with power dissipation of just 440mW. When the device is deselected,the CMOS standby current is less than 200μA.
The AT28C256 is accessed like a Static RAM for the read or write cycle without the need for external components. The device contains a 64-byte page register to allow writing of up to 64 bytes simultaneously. During a write cycle, the addresses and 1 to 64 bytes of data are internally latched, freeing the address and data bus for other operations. Following the initiation of a write cycle, the device will automatically write the latched data using an internal control timer.The end of a write cycle can be detected by DATA Polling of I/O7.Once the end of a write cycle has been detected a new access for a read or write can begin.
Atmel's AT28C256 has additional features to ensure high quality and manufacturability.The device utilizes internal error correction for extended endurance and improved data retention characteristics.An optional software data protection mechanism is available to guard against inadvertent writes.The device also includes an extra 64 bytes of EEPROM for device identification or tracking.
