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製品の説明
The AD7731 is a complete analog front-end for process control applications. The device has a proprietary programmable gain front end that allows it to accept a range of input signal ranges, including low level signals, directly from a transducer. The sigmadelta architecture of the part consists of an analog modulator and a low pass programmable digital filter, allowing adjustment of filter cutoff, output rate and settling time. The part features three buffered differential programmable gain analog inputs (which can be configured as five pseudo-differential inputs), as well as a differential reference input. The part operates from a single +5 V supply and accepts seven unipolar analog input ranges: 0 to +20 mV, +40 mV, +80 mV, +160 mV, +320 mV, +640 mV and +1.28 V, and seven bipolar ranges: ±20 mV, ±40 mV, ±80 mV, ±160 mV, ±320 mV, ±640 mV and ±1.28 V. The peak-to-peak resolution achievable directly from the part is 16 bits at an 800 Hz output rate. The part can switch between channels with 1 ms settling time and maintain a performance level of 13 bits of peak-to-peak resolution. The serial interface on the part can be configured for three-wire operation and is compatible with microcontrollers and digital signal processors. The AD7731 contains self-calibration and system calibration options and features an offset drift of less than 5 nV/°C and a gain drift of less than 2 ppm/°C. The part is available in a 24-lead plastic DIP, a 24-lead SOIC and 24-lead TSSOP package. Applications Process Control PLCs/DCS Industrial Instrumentation
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FEATURES 24-Bit Sigma-Delta ADC 16 Bits p-p Resolution 800 Hz Output Rate Programmable Output Rates to 6.4 kHz Programmable Gain Front End 0.0015% Nonlinearity Buffered Differential Inputs Programmable Filter Cutoffs FASTStepTM* Mode for Channel Sequencing Single Supply Operation
APPLICATIONS Process Control PLCs/DCS Industrial InstrumentationGENERAL DESCRIPTION The is a complete analog front-end for process control applications. The device has a proprietary programmable gain front end that allows it to accept a range of input signal ranges, including low level signals, directly from a transducer. The sigmadelta architecture of the part consists of an analog modulator and a low pass programmable digital filter, allowing adjustment of filter cutoff, output rate and settling time.
The part features three buffered differential programmable gain analog inputs (which can be configured as five pseudo-differential inputs), as well as a differential reference input. The part operates from a single +5 V supply and accepts seven unipolar analog input ranges: to +20 mV, +40 mV, +80 mV, +160 mV, +320 mV, +640 mV and +1.28 V, and seven bipolar ranges: ± 20 mV, ± 40 mV, ± 80 mV, ± 160 mV, ± 320 mV, 640 mV and 1.28 V. The peak-to-peak resolution achievable directly from the part is 16 bits 800 Hz output rate. The part can switch between channels with 1 ms settling time and maintain a performance level of 13 bits of peak-to-peak resolution.
The serial interface on the part can be configured for three-wire operation and is compatible with microcontrollers and digital signal processors. The AD7731 contains self-calibration and system calibration options and features an offset drift of less than 5 nV/°C and a gain drift of less than 2 ppm/°C.
The part is available a 24-lead plastic DIP, a 24-lead SOIC and 24-lead TSSOP package.Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
AD7731SPECIFICATIONS (AVDD +5 V, DVDD +5 V; REF IN(+) +2.5 V; REF IN() = AGND; AGND = DGND 0 V; fCLK = 4.9152 MHz. All specifications TMIN to TMAX unless otherwise noted.)
STATIC PERFORMANCE (CHP 0) No Missing Codes2 Output Noise and Update Rates2 Integral Nonlinearity Offset Error2 Offset Drift vs. Temperature2
Offset Drift vs. Time5 Positive Full-Scale Error2, 6 Positive Full-Scale Drift vs. 7, 8Positive Full-Scale Drift vs. Time5 Gain Error2, 9 Gain Drift vs. 7, 10 Gain Drift vs. Time5 Bipolar Negative Full-Scale Error2 Negative Full-Scale Drift vs. Temp2, 7 Power Supply Rejection11 Power Supply Rejection11 Common-Mode Rejection (CMR)11
On AIN On AIN On REF IN Analog Input DC Bias Current2 Analog Input DC Bias Current Drift2 Analog Input DC Offset Current2 Analog Input DC Offset Current Drift2
Offset Error and Offset Drift Refer to Both Input Range = 20 mV, 40 mV, 80 mV, 160 mV Input Range mV/1.28 V
Input Range 20 mV Input Range V At DC. Input Range mV At DC. Input Range 1.28 VOffset Drift vs. Temperature Offset Drift vs. Time5 Positive Full-Scale Error6 Positive Full-Scale Drift vs. Temp7, 8 Positive Full-Scale Drift vs. Time5 Gain Error9 Gain Drift vs. Temperature7, 10 Gain Drift vs. Time5
Negative Full-Scale Drift vs. Temp Power Supply Rejection11 Power Supply Rejection11 Common-Mode Rejection (CMR)11
Offset Error and Offset Drift Refer to Both Unipolar Offset and Bipolar Zero ErrorsAssuming 5 V Reference with HIREF Bit Set Appropriately RN0 of Mode Register RN0 of Mode Register RN0 of Mode Register RN0 of Mode Register RN0 of Mode Register RN0 of Mode Register RN0 of Mode Register
Reference Input REF IN(+) REF IN Voltage REF IN(+) REF IN Voltage Reference DC Input Current Reference DC Input Current Absolute/Common-Mode Voltage14
VINL, Input Low Voltage VINL, Input Low Voltage VINH, Input High Voltage SCLK Only (Schmitt Triggered Input)
VINL, Input Low Voltage VINL, Input Low Voltage VINH, Input High Voltage VINH, Input High VoltagePOWER REQUIREMENTS Power Supply Voltages AVDD AGND Voltage DVDD Voltage Power Supply Currents AVDD Current (Normal Mode) DVDD Current (Normal Mode) DVDD Current (Normal Mode) AVDD + DVDD Current (Standby Mode) Power Dissipation Normal Mode Standby Mode
V min/V max V min/V max V min/V max V min/V max V min/V max V min/V maxHIREF Bit of Mode Register = 0 HIREF Bit of Mode Register = 1 HIREF Bit of Mode Register = 0 HIREF Bit of Mode Register = 1
NO REF Bit Active If VREF Below This Voltage NO REF Bit Inactive If VREF Above This VoltageISINK 800 µA Except for MCLK +5 V ISINK 100 µA Except for MCLK +3 V ISOURCE 200 µA Except for MCLK +5 V ISOURCE 100 µA Except for MCLK +3 V
With AGND 0 V External MCLK. Digital I/Ps V or DVDD 3.3 V DVDD 5.25 V Typically 10 µA. External MCLK V or DVDD AVDD = DVDD +5 V. Digital I/Ps V or DVDD Typically 50 µW. External MCLK V or DVDD
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Japan からの 44 件のバイヤーレビュー
Brandon Robinson
Length of registration:7 years
The AD7731BRZ is an integrated circuit from Analog Devices that offers high performance for applications requiring precision analog-to-digital conversion. It features a 24-bit resolution, low power consumption, and a wide input range. It also offers a high level of accuracy, with a maximum total unadjusted error of 0.5LSB. Additionally, it is designed to operate in temperatures ranging from -40°C
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03/17/2023
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AD7731BRZ
AD7731BRZには世界中にいくつかのブランドがあり、地域の違いや買収によりAD7731BRZの別名が付けられる場合があります。 AD7731BRZは次の名前でも知られています。
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