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Description
3.3V 144-mc CPLD
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Features
● 5 ns pin-to-pin logic delays
● System frequency up to 178 MHz
● 144 macrocells with 3,200 usable gates
● Available in small footprint packages
— 100-pin TQFP (81 user I/O pins)
— 144-pin TQFP (117 user I/O pins)
— 144-CSP (117 user I/O pins)
— Pb-free available for all packages
● Optimized for high-performance 3.3V systems
— Low power operation
— 5V tolerant I/O pins accept 5V, 3.3V, and 2.5V signals
— 3.3V or 2.5V output capability
— Advanced 0.35 micron feature size CMOS Fast FLASHTM technology
● Advanced system features
— In-system programmable
— Superior pin-locking and routability with Fast CONNECTTM II switch matrix
— Extra wide 54-input Function Blocks
— Up to 90 product-terms per macrocell with individual product-term allocation
— Local clock inversion with three global and one product-term clocks
— Individual output enable per output pin with local inversion
— Input hysteresis on all user and boundary-scan pin inputs
— Bus-hold circuitry on all user pin inputs
— Full IEEE Standard 1149.1 boundary-scan (JTAG)
● Fast concurrent programming
● Slew rate control on individual outputs
● Enhanced data security features
● Excellent quality and reliability
— Endurance exceeding 10,000 program/erase cycles
— 20 year data retention
— ESD protection exceeding 2,000V
● Pin-compatible with 5V-core XC95144 device in the 100-pin TQFP package
WARNING: Programming temperature range of TA = 0℃ to +70℃
Description
The XC95144XL is a 3.3V CPLD targeted for high-performance, low-voltage applications in leading-edge communications and computing systems. It is comprised of eight 54V18 Function Blocks, providing 3,200 usable gates with propagation delays of 5 ns.
Power Estimation
Power dissipation in CPLDs can vary substantially depending on the system frequency, design application and output loading. To help reduce power dissipation, each macrocell in a XC9500XL device may be configured for low-power mode (from the default high-performance mode). In addition, unused product-terms and macrocells are automatically deactivated by the software to further conserve power. For a general estimate of ICC, the following equation may be used:
ICC(mA) = MCHS(0.175*PTHS + 0.345) + MCLP(0.052*PTLP+ 0.272) + 0.04 * MCTOG(MCHS +MCLP)* f
where:
MCHS = # macrocells in high-speed configuration
PTHS = average number of high-speed product terms per macrocell
MCLP = # macrocells in low power configuration
PTLP = average number of low power product terms per macrocell
f = maximum clock frequency
MCTOG = average % of flip-flops toggling per clock (~12%)
This calculation was derived from laboratory measurements of an XC9500XL part filled with 16-bit counters and allowing a single output (the LSB) to be enabled. The actual ICC value varies with the design application and should be verified during normal system operation.
Preview of the first 3 pages of the data sheet
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6 buyer reviews from Philippines
Mary Johnson
Length of registration:7 years
I recently ordered an IC XC95144XL-10TQG100C from your company and I am very pleased with the product. The IC is highly reliable and offers excellent performance. The features are very impressive and the integration of the IC with other components is seamless. The instructions provided for installation and use are very clear and easy to understand. I am very satisfied with the product and would de
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03/17/2023
Mariusz Adamus
Length of registration:7 years
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02/04/2018
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XC95144XL-10TQG100C
XC95144XL-10TQG100C has several brands around the world that may have alternate names for XC95144XL-10TQG100C due to regional differences or acquisition. XC95144XL-10TQG100C may also be known as the following names:
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Unit Price:352.11827
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