ADS7807U

FEATURES

q 35mW max POWER DISSIPATION q 50µW POWER-DOWN MODE q 25µs max ACQUISITION AND CONVERSION q ±1.5LSB max INL q DNL: 16 Bits, No Missing Codes q 86dB min SINAD WITH 1kHz INPUT TO +5V, AND TO +4V INPUT RANGES q SINGLE +5V SUPPLY OPERATION q PARALLEL AND SERIAL DATA OUTPUT q PIN-COMPATIBLE WITH THE ADS7806 q USES INTERNAL OR EXTERNAL REFERENCE 0.3" DIP-28 AND SO-28

DESCRIPTION

The is a low-power, 16-bit, sampling Analog-toDigital (A/D) converter using state-of-the-art CMOS structures. It contains a complete 16-bit, capacitor-based, Successive Approximation Register (SAR) A/D converter with sample-and-hold, clock, reference, and microprocessor interface with parallel and serial output drivers.

The ADS7807 can acquire and convert 16 bits to within in 25µs max while consuming only 35mW max. Laser trimmed scaling resistors provide standard industrial input ranges of ±10V and +5V. In addition, to +4V range allows development of complete single-supply systems.

The ADS7807 is available 0.3" DIP-28 and SO-28, both fully specified for operation over the industrial to +85°C temperature range.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

Analog Inputs: : ±5.5V CAP : VANA ­ 0.3V REF : Indefinite Short to AGND2, Momentary Short to VANA

Ground Voltage Differences: DGND, AGND1, and : ±0.3V VANA : 7V VDIG to VANA : +0.3V VDIG : 7V Digital Inputs ­0.3V to VDIG + 0.3V Maximum Junction Temperature : +165°C Internal Power Dissipation : 825mW Lead Temperature (soldering, : +300°C

NOTE: (1) Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Exposure to absolute maximum conditions for extended periods may affect device reliability.

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

NOTE: (1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com.

= 40kHz, VDIG = VANA = +5V, and using internal reference and fixed resistors (see Figure 7b), unless otherwise specified.

ANALOG INPUT Voltage Ranges Impedance Capacitance
THROUGHPUT SPEED Conversion Time Complete Cycle Throughput Rate

DC ACCURACY Integral Linearity Error Differential Linearity Error No Missing Codes Transition Noise(2) Gain Error Full-Scale Error(3,4) Full-Scale Error Drift Full-Scale Error(3,4) Full-Scale Error Drift Bipolar Zero Error(3) Bipolar Zero Error Drift Unipolar Zero Error(3) Unipolar Zero Error Drift Recovery Time to Rated Accuracy

= 40kHz, VDIG = VANA = +5V, and using internal reference and fixed resistors (see Figure 7b), unless otherwise specified.

AC ACCURACY Spurious-Free Dynamic Range Total Harmonic Distortion Signal-to-(Noise + Distortion)
SAMPLING DYNAMICS Aperture Delay Aperture Jitter Transient Response Over-Voltage Recovery(8)
REFERENCE Internal Reference Voltage Internal Reference Source Current
(Must use external buffer.) Internal Reference Drift External Reference Voltage Range
for Specified Linearity External Reference Current Drain
DIGITAL OUTPUTS Data Format Data Coding
Parallel 16 bits in 2-bytes; Serial Binary Two's Complement or Straight Binary
DIGITAL TIMING Bus Access Time Bus Relinquish Time
VDIG VANA IDIG IANA Power Dissipation
TEMPERATURE RANGE Specified Performance Derated Performance Storage Thermal Resistance (JA)

NOTES: (1) LSB means Least Significant Bit. One LSB for the ±10V input range 305µV. (2) Typical rms noise at worst-case transition. (3) As measured with fixed resistors, see Figure 7b. Adjustable to zero with external potentiometer. (4) Full-scale error is the worst case of ­Full-Scale or +Full-Scale untrimmed deviation from ideal first and last code transitions, divided by the transition voltage (not divided by the full-scale range) and includes the effect of offset error. (5) This is the time delay after the ADS7807 is brought out of Power-Down mode until all internal settling occurs and the analog input is acquired to rated accuracy. A Convert command after this delay will yield accurate results. (6) All specifications in dB are referred to a full-scale input. (7) Usable bandwidth defined as full-scale input frequency at which Signal-to-(Noise + Distortion) degrades 60dB. (8) Recovers to specified performance after 2 FS input overvoltage. (9) The minimum VIH level for the DATACLK signal is 3V.